At times, semantically equivalent code, written in two different ways, might cause the optimizer to have a more difficult time performing good register allocation. 有时,语义上等同但采用两种不同方式编写的代码可能会使优化器在执行良好的寄存器分配上所花费的时间相差巨大。
The CLR JIT can only track a fixed number of variables for register allocation; once it has to track more than this, it begins to spill the contents of registers into memory. CLRJIT只能跟踪固定数目的寄存器分配变量;一旦需要跟踪的数目超出这个数目,它就开始将寄存器的内容移到内存中。
Loop unrolling done by the C++ compiler can expose more instruction-level parallelism, but can also create more live variables that the optimizer needs to track for register allocation. C++编译器完成的循环展开可以公开更多的指令级并行,但也创建了更多活变量(livevariable),编译器需要使用它们来跟踪寄存器分配。
Critical Techniques for Register Allocation on IXP Network Processors IXP网络处理器寄存器分配的关键技术
Technique of applying Feedback-Directed compiling optimization in register allocation 反馈式编译优化在寄存器分配中的应用技术
Integration of instruction scheduling and register allocation 指令调度和寄存器分配的集成算法
A Study on Register Allocation in High-Level Synthesis 高级综合中寄存器分配问题的研究
Combine Register Allocation with Instruction Scheduling by Register Queue Model 通过寄存器队列模型实现寄存器分配和指令调度
And then the traditional register allocation procedure is improved, and a new algorithm for constructing refined interference graph is presented. 然后在其基础上,对传统寄存器分配算法进行改进,给出了一种建立精化干涉图的新算法;
Firstly, this paper proposes a modified register allocation via graph coloring to alleviate port conflicts. 然后,面对分体寄存器文件可能产生端口冲突的新问题,提出了改进的基于图着色的寄存器分配法。
This thesis attacks two important issues in back end of an optimizing compiler: instruction selection and register allocation. 这篇论文尝试解决优化编译器的后端中的两个重要的问题:指令选择和寄存器分配。
Then, it puts forward a chain-based IR when considering the demand of data flow analysis, instruction scheduling and register allocation. At last, an algorithm is given. 结合编译器中数据流分析,指令调度和寄存器分配的需求,进一步提出了一种基于链表结构的中间表示及构造算法。
Register allocation and code generation are key parts of generating high performance assembly code. 寄存器分配和代码生成是决定编译器能否生成高效代码的关键部分。
And a translation-guided algorithm for register allocation. 翻译制导的寄存器优化算法。
Register allocation is a key field relating to the efficiency of a binary translator. 寄存器的使用效率是决定程序性能的关键因素之一,本文提出了适用于动态二进制翻译的翻译制导寄存器分配方法。
This paper presents an integrated instruction scheduling and register allocation algorithm for processors with an extended delayed-load architecture. 基于扩展的装入延时体系结构模型,提出了在代码生成过程中针对表达式树的森林的局部寄存器分配和局部指令调度的集成算法。
And based on traditional graph coloring register allocation, a new algorithm to construct unified and simplified interference graph utilizing complementary predicate is presented, which can reduce spill code. 对传统着色图寄存器分配算法进行改进,给出了一种利用互补谓词机制建立统一简化干涉图的新算法,减少了代码溢出;
Register allocation and instruction scheduling are two important tasks for every optimizing compiler. 寄存器分配与指令调度是编译器优化过程中的两项重要任务。
A new register allocation algorithm for predicated code is proposed. 提出了适于谓词执行的寄存器分配算法。
Spill code sensitive learning and spill code hot function sensitive learning are given based on the idea of fast machine learning method for register allocation. 根据基于静态分析的快速机器学习思想,本文就寄存器分配提出了两种快速机器学习方法:溢出代码敏感的机器学习和溢出代码与热函数敏感的机器学习。
Register allocation can be divided into twocategories: global register allocation and local register allocation. 寄存器分配算法可以分为两大类:全局寄存器分配算法和局部寄存器分配算法。
Propose a register allocation framework for machines with connected and partitioned register banks. 提出了一种相连多寄存器组结构上的寄存器分配方法。
In the present paper we introduce a new variant of the hybrid method for multiple-precision multiplication that optimizes both memory accesses and register allocation. 在本硕士毕业论文中,我们提出了一种新的基于多精度乘法的混合乘算法,这种新的混合乘算法不仅可以优化内存的访问次数还可以优化寄存器的分配问题。
The thesis presents a memory coloring ( memory partition plus graph coloring register allocation) based SRF allocation framework. 本文提出了一套基于存储器着色(即存储器划分加上图着色寄存器分配)技术的SRF分配框架。
Present the cooperative instruction scheduling: aim at the phase-ordering problem of instruction scheduling and register allocation. ◆提出协作式指令调度方法:针对寄存器分配与指令调度的时序问题,提出一种协作式指令调度方法。
The novelty in our research lies in the integration of reuse exploitation and parallelism exploitation into the classic graph coloring register allocation framework. 本文研究的新颖之处在于将开发重用和并行巧妙地整合到传统的图着色寄存器分配框架中。
Register allocation on this kind of processors is a big challenge for compilers. 在这类处理器上分配好寄存器是对编译器的一大挑战。
By processing the allocation of group and the allocation of register separately, we simplify the interference graph and reduce the complexity of register allocation. 这一划分简化了干涉图,降低了寄存器分配的复杂度。
IXP compiler must deal with register allocation as well as bank assignment, due to the constraint above. 由于上面的限制,IXP网络处理器不仅需要处理寄存器分配问题,还要处理组分配问题。
Besides, we modify the cluster assigning and register allocation for complex operations. 除此之外,我们还在分簇和寄存器分配模块为复数运算做了相应的修改。